1. Field of the Invention
The present invention relates generally to the field of ramp signal generators. In one aspect, the present invention relates to a circuit and method for generating ramped voltage signals having stable maximum amplitude.
2. Description of the Related Art
Ramp generator circuits are used to generate ramped voltages for various applications, such as pulse width modulated converters, DC-DC converters, built-in self test (BIST) circuits, sawtooth generators, etc. However, convention servo-controlled voltage ramp generators are unduly complex in terms of the circuit design and operation, thereby using valuable silicon area and consuming excessive power. For example, conventional ramp generators require that multiple clock phases be provided to the ramp generator, and/or that the provided clock frequencies are higher than the ramp signal frequency. In addition, conventional solutions require accurate pulse widths for use in monitoring and correcting the ramp signal, and also require that the ramp monitoring and correction steps be performed at same time (which can impair linearity). Another problem with conventional ramp generators is that the amplitude of the ramp signal depends on the input clock frequency, and therefore can vary variation as the input frequency changes. Yet another drawback with prior ramp generators is that the maximum or peak voltage of the ramp signal is constrained by the input reference voltage. These design and performance limitations not only result in large and inefficient designs, but also impose additional system costs where, for example, a high to medium precision digital-to-analog converter must be used.
To provide an example of a conventional ramp generator circuit, reference is now made to FIG. 1 which depicts a ramped voltage generator 10 described in U.S. Pat. No. 6,169,433 to Farrenkopf wherein an operational transconductance amplifier 2 receiving a reference voltage is enabled by an input clock signal to drive a ramped voltage generation circuit 4 that produces a ramped voltage signal V3 that is fed back to the amplifier 2. The ramped voltage signal V3 is corrected or reset by the one-shot circuit 6 which receives, wherein input clock that enables the amplifier 2 also drives a one-shot circuit 6 which produces, in response to the input clock signal, a delayed voltage pulse train which is applied to discharge a capacitor C2 in the ramped voltage generation circuit 4 that is periodically charged and discharged to generate the ramped voltage V3. As shown in FIG. 2, the ramped voltage generator 10 receives the input clock signal 21 and generates therefrom the reset pulse signal 22 (which corresponds to the output V2 of the one-shot circuit 6). In response to the input clock signal 21, the ramped voltage generation circuit 4 produces the ramp signal 23 (which corresponds to the ramped voltage signal V3). While the input clock signal 21 is “high,” the ramped voltage signal V3 is sampled, and when the reset pulse signal 22 is “high,” the capacitor C2 is reset.
As this example shows, the sampling (monitoring) and reset (correction) events occur at same time, which can cause ramp distortion and decrease linearity, depending on the ramp period and clock pulse width. Given the temporal proximity of the clocking signals, the conventional ramped voltage generators require well synchronized and very accurate multi-phase pulse widths in order to monitor/adjust the ramp amplitude. Accordingly, there is a need for an improved voltage ramp generator circuit and methodology to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.